604 lines
21 KiB
C++
604 lines
21 KiB
C++
// main.cpp
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#include <cstdio>
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#include <cstdint>
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#include <cstring>
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#include <sstream>
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#include <string>
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#include <vector>
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#include <chrono>
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#include <thread>
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// OpenGL/GLFW and GLEW headers.
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#include <GL/glew.h>
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#include <GLFW/glfw3.h>
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// ImGui headers.
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#include "imgui.h"
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#include "imgui_impl_glfw.h"
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#include "imgui_impl_opengl3.h"
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#include "out.h"
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// --------------------------------------------------------------------------------
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// CPU Flags structure (for debugging and visualization)
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// --------------------------------------------------------------------------------
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struct CPUFlags {
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bool zero;
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bool negative;
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bool carry;
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bool overflow;
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};
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// --------------------------------------------------------------------------------
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// RISC-V Emulator Class.
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// This example implements a subset of the RV32I instructions plus ECALL for
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// basic system calls that print data to a virtual terminal.
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class RiscVEmulator {
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public:
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// 32 general-purpose registers and the program counter.
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uint32_t registers[32];
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uint32_t pc;
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// Memory implemented as an array of 32-bit words.
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std::vector<uint32_t> memory;
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// CPU flags for arithmetic operations.
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CPUFlags flags;
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// A flag to halt execution in case of error.
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bool halted;
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// A buffer to collect terminal output (our “screen”).
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std::string terminalOutput;
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// Constructor: allocate memory (memSize in words) and reset the CPU.
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RiscVEmulator(size_t memSize)
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: pc(0), memory(memSize, 0), halted(false)
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{
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reset();
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}
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// Reset CPU state and (optionally) memory.
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void reset() {
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pc = 0;
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std::memset(registers, 0, sizeof(registers));
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flags = { false, false, false, false };
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halted = false;
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terminalOutput.clear();
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}
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// Load a program (vector of 32-bit instructions) into memory.
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void loadProgram(const std::vector<uint32_t>& program) {
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for (size_t i = 0; i < program.size() && i < memory.size(); i++) {
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memory[i] = program[i];
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}
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}
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// Helper to update flags on addition.
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void updateFlagsForAddition(uint32_t op1, uint32_t op2, uint32_t result) {
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flags.zero = (result == 0);
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flags.negative = (static_cast<int32_t>(result) < 0);
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flags.carry = (result < op1);
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bool sign1 = (static_cast<int32_t>(op1) < 0);
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bool sign2 = (static_cast<int32_t>(op2) < 0);
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bool signr = (static_cast<int32_t>(result) < 0);
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flags.overflow = ((sign1 == sign2) && (signr != sign1));
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}
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// Helper to update flags on subtraction.
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void updateFlagsForSubtraction(uint32_t op1, uint32_t op2, uint32_t result) {
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flags.zero = (result == 0);
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flags.negative = (static_cast<int32_t>(result) < 0);
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flags.carry = (op1 < op2);
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bool sign1 = (static_cast<int32_t>(op1) < 0);
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bool sign2 = (static_cast<int32_t>(op2) < 0);
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bool signr = (static_cast<int32_t>(result) < 0);
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flags.overflow = ((sign1 != sign2) && (signr != sign1));
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}
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// Helper: Read a null-terminated string from memory starting at the given address.
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// This function assumes that the string is stored in little-endian order.
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std::string readString(uint32_t address) {
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std::string result;
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while (true) {
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if (address / 4 >= memory.size())
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break;
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uint32_t word = memory[address / 4];
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// Extract 4 bytes from the word.
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for (int i = 0; i < 4; i++) {
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char ch = (char)((word >> (i * 8)) & 0xFF);
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if (ch == '\0') return result;
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result.push_back(ch);
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}
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address += 4;
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}
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return result;
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}
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// Execute one instruction (fetch-decode-execute).
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void step() {
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if (halted) return;
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if (pc % 4 != 0 || (pc / 4) >= memory.size()) {
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halted = true;
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return;
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}
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uint32_t inst = memory[pc / 4];
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uint32_t opcode = inst & 0x7F;
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switch (opcode) {
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// R-type instructions.
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case 0x33: {
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uint32_t rd = (inst >> 7) & 0x1F;
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uint32_t rs1 = (inst >> 15) & 0x1F;
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uint32_t rs2 = (inst >> 20) & 0x1F;
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uint32_t funct3 = (inst >> 12) & 0x7;
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uint32_t funct7 = (inst >> 25) & 0x7F;
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switch (funct3) {
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case 0x0:
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if (funct7 == 0x00) { // ADD
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uint32_t res = registers[rs1] + registers[rs2];
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registers[rd] = res;
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updateFlagsForAddition(registers[rs1], registers[rs2], res);
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} else if (funct7 == 0x20) { // SUB
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uint32_t res = registers[rs1] - registers[rs2];
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registers[rd] = res;
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updateFlagsForSubtraction(registers[rs1], registers[rs2], res);
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}
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break;
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case 0x1: // SLL
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registers[rd] = registers[rs1] << (registers[rs2] & 0x1F);
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break;
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case 0x2: // SLT
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registers[rd] = ((int32_t)registers[rs1] < (int32_t)registers[rs2]) ? 1 : 0;
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break;
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case 0x3: // SLTU
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registers[rd] = (registers[rs1] < registers[rs2]) ? 1 : 0;
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break;
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case 0x4: // XOR
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registers[rd] = registers[rs1] ^ registers[rs2];
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break;
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case 0x5:
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if (funct7 == 0x00) { // SRL
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registers[rd] = registers[rs1] >> (registers[rs2] & 0x1F);
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} else if (funct7 == 0x20) { // SRA
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registers[rd] = ((int32_t)registers[rs1]) >> (registers[rs2] & 0x1F);
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}
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break;
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case 0x6: // OR
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registers[rd] = registers[rs1] | registers[rs2];
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break;
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case 0x7: // AND
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registers[rd] = registers[rs1] & registers[rs2];
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break;
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}
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pc += 4;
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break;
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}
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// I-type arithmetic instructions.
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case 0x13: {
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uint32_t rd = (inst >> 7) & 0x1F;
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uint32_t rs1 = (inst >> 15) & 0x1F;
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uint32_t funct3 = (inst >> 12) & 0x7;
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int32_t imm = ((int32_t)inst) >> 20;
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switch (funct3) {
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case 0x0: { // ADDI
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uint32_t res = registers[rs1] + imm;
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registers[rd] = res;
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updateFlagsForAddition(registers[rs1], imm, res);
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break;
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}
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case 0x2: // SLTI
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registers[rd] = (((int32_t)registers[rs1]) < imm) ? 1 : 0;
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break;
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case 0x3: // SLTIU
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registers[rd] = (registers[rs1] < (uint32_t)imm) ? 1 : 0;
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break;
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case 0x4: // XORI
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registers[rd] = registers[rs1] ^ imm;
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break;
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case 0x6: // ORI
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registers[rd] = registers[rs1] | imm;
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break;
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case 0x7: // ANDI
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registers[rd] = registers[rs1] & imm;
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break;
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case 0x1: { // SLLI
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uint32_t shamt = imm & 0x1F;
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registers[rd] = registers[rs1] << shamt;
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break;
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}
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case 0x5: {
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uint32_t shamt = imm & 0x1F;
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uint32_t imm_high = (inst >> 25) & 0x7F;
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if (imm_high == 0x00) { // SRLI
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registers[rd] = registers[rs1] >> shamt;
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} else if (imm_high == 0x20) { // SRAI
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registers[rd] = ((int32_t)registers[rs1]) >> shamt;
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}
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break;
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}
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}
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pc += 4;
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break;
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}
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// Branch instructions (B-type).
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case 0x63: {
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uint32_t rs1 = (inst >> 15) & 0x1F;
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uint32_t rs2 = (inst >> 20) & 0x1F;
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uint32_t funct3 = (inst >> 12) & 0x7;
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int32_t imm = (((inst >> 31) & 0x1) << 12) |
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(((inst >> 25) & 0x3F) << 5) |
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(((inst >> 8) & 0xF) << 1) |
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(((inst >> 7) & 0x1) << 11);
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if (imm & (1 << 12))
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imm |= 0xFFFFE000;
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switch (funct3) {
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case 0x0: // BEQ
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pc = (registers[rs1] == registers[rs2]) ? (pc + imm) : (pc + 4);
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break;
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case 0x1: // BNE
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pc = (registers[rs1] != registers[rs2]) ? (pc + imm) : (pc + 4);
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break;
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case 0x4: // BLT
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pc = (((int32_t)registers[rs1]) < ((int32_t)registers[rs2])) ? (pc + imm) : (pc + 4);
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break;
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case 0x5: // BGE
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pc = (((int32_t)registers[rs1]) >= ((int32_t)registers[rs2])) ? (pc + imm) : (pc + 4);
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break;
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case 0x6: // BLTU
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pc = (registers[rs1] < registers[rs2]) ? (pc + imm) : (pc + 4);
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break;
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case 0x7: // BGEU
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pc = (registers[rs1] >= registers[rs2]) ? (pc + imm) : (pc + 4);
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break;
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}
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break;
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}
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// JAL: J-type jump.
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case 0x6F: {
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uint32_t rd = (inst >> 7) & 0x1F;
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int32_t imm = (((inst >> 31) & 0x1) << 20) |
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(((inst >> 21) & 0x3FF) << 1) |
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(((inst >> 20) & 0x1) << 11) |
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(((inst >> 12) & 0xFF) << 12);
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if (imm & (1 << 20))
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imm |= 0xFFF00000;
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registers[rd] = pc + 4;
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pc += imm;
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break;
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}
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// JALR: I-type jump.
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case 0x67: {
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uint32_t rd = (inst >> 7) & 0x1F;
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uint32_t rs1 = (inst >> 15) & 0x1F;
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int32_t imm = ((int32_t)inst) >> 20;
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uint32_t temp = pc + 4;
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pc = (registers[rs1] + imm) & ~1;
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registers[rd] = temp;
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break;
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}
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// LUI: U-type.
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case 0x37: {
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uint32_t rd = (inst >> 7) & 0x1F;
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registers[rd] = inst & 0xFFFFF000;
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pc += 4;
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break;
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}
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// AUIPC: U-type.
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case 0x17: {
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uint32_t rd = (inst >> 7) & 0x1F;
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registers[rd] = pc + (inst & 0xFFFFF000);
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pc += 4;
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break;
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}
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// Load instructions (LW only).
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case 0x03: {
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uint32_t rd = (inst >> 7) & 0x1F;
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uint32_t rs1 = (inst >> 15) & 0x1F;
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uint32_t funct3 = (inst >> 12) & 0x7;
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int32_t imm = ((int32_t)inst) >> 20;
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if (funct3 == 0x2) { // LW
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uint32_t addr = registers[rs1] + imm;
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if (addr % 4 == 0 && (addr / 4) < memory.size())
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registers[rd] = memory[addr / 4];
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}
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pc += 4;
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break;
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}
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// Store instructions (SW only).
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case 0x23: {
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uint32_t rs1 = (inst >> 15) & 0x1F;
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uint32_t rs2 = (inst >> 20) & 0x1F;
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uint32_t funct3 = (inst >> 12) & 0x7;
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int32_t imm = (((inst >> 25) & 0x7F) << 5) | ((inst >> 7) & 0x1F);
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if (imm & 0x800) imm |= 0xFFFFF000;
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if (funct3 == 0x2) { // SW
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uint32_t addr = registers[rs1] + imm;
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if (addr % 4 == 0 && (addr / 4) < memory.size())
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memory[addr / 4] = registers[rs2];
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}
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pc += 4;
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break;
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}
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// ECALL: Opcode 0x73 (environment call).
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// This branch simulates interrupts/system calls to “print” data to our terminal.
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case 0x73: {
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// For ECALL, we follow a simple convention:
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// - Register x17 (a7) holds the system call number.
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// - Register x10 (a0) holds the argument.
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// Conventions used below:
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// 1: Print integer (from x10).
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// 2: Print character (the low-order 8 bits of x10).
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// 3: Print string (address pointer stored in x10).
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uint32_t funct3 = (inst >> 12) & 0x7;
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if (funct3 == 0) {
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uint32_t syscall = registers[17]; // a7
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switch (syscall) {
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case 1: { // Print integer.
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int value = (int) registers[10]; // a0
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terminalOutput += std::to_string(value) + "\n";
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break;
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}
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case 2: { // Print character.
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char ch = (char)(registers[10] & 0xFF);
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terminalOutput.push_back(ch);
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break;
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}
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case 3: { // Print string (pointer in a0).
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std::string str = readString(registers[10]);
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terminalOutput += str;
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break;
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}
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default:
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terminalOutput += "Unknown ECALL: " + std::to_string(syscall) + "\n";
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break;
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}
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}
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pc += 4;
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break;
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}
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default:
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// Unknown opcode – halt the CPU.
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halted = true;
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break;
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}
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// Enforce that register x0 is always 0.
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registers[0] = 0;
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}
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// Disassemble an instruction at the given address.
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std::string disassembleInstruction(uint32_t address) {
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if (address % 4 != 0 || (address / 4) >= memory.size())
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return "Invalid address";
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uint32_t inst = memory[address / 4];
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uint32_t opcode = inst & 0x7F;
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std::stringstream ss;
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ss << "0x" << std::hex << inst << std::dec << " ";
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switch (opcode) {
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case 0x33: { // R-type
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uint32_t rd = (inst >> 7) & 0x1F;
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uint32_t rs1 = (inst >> 15) & 0x1F;
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uint32_t rs2 = (inst >> 20) & 0x1F;
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uint32_t funct3 = (inst >> 12) & 0x7;
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uint32_t funct7 = (inst >> 25) & 0x7F;
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if (funct3 == 0x0 && funct7 == 0x00)
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ss << "ADD x" << rd << ", x" << rs1 << ", x" << rs2;
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else if (funct3 == 0x0 && funct7 == 0x20)
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ss << "SUB x" << rd << ", x" << rs1 << ", x" << rs2;
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else
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ss << "R-type (0x" << std::hex << inst << ")";
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break;
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}
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case 0x13:
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ss << "ADDI (or other I-type)";
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break;
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case 0x63:
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ss << "Branch/Compare";
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break;
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case 0x6F:
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ss << "JAL";
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break;
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case 0x67:
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ss << "JALR";
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break;
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case 0x37:
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ss << "LUI";
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break;
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case 0x17:
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ss << "AUIPC";
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break;
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case 0x03:
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ss << "LW";
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break;
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case 0x23:
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ss << "SW";
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break;
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case 0x73:
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ss << "ECALL";
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break;
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default:
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ss << "Unknown opcode";
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break;
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}
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return ss.str();
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}
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};
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// --------------------------------------------------------------------------------
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// Main: OpenGL/GLFW + ImGui Debugger and Terminal UI.
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// --------------------------------------------------------------------------------
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int main(int, char**) {
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// Initialize GLFW.
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if (!glfwInit()) {
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fprintf(stderr, "Failed to initialize GLFW\n");
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return 1;
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}
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const char* glsl_version = "#version 130";
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glfwWindowHint(GLFW_CONTEXT_VERSION_MAJOR, 3);
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glfwWindowHint(GLFW_CONTEXT_VERSION_MINOR, 0);
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GLFWwindow* window = glfwCreateWindow(1280, 720, "RISC-V Emulator with Terminal", NULL, NULL);
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if (window == nullptr)
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return 1;
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glfwMakeContextCurrent(window);
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glfwSwapInterval(1);
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// Initialize ImGui.
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IMGUI_CHECKVERSION();
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ImGui::CreateContext();
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ImGuiIO& io = ImGui::GetIO(); (void)io;
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ImGui::StyleColorsDark();
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ImGui_ImplGlfw_InitForOpenGL(window, true);
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ImGui_ImplOpenGL3_Init(glsl_version);
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// Create the emulator instance with 1024 words of memory.
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RiscVEmulator emulator(1024);
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emulator.loadProgram(program_data);
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// Debugger control flags.
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bool running = false;
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double lastStepTime = glfwGetTime();
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const double stepInterval = 0.1; // Auto-step every 0.1 sec in "running" mode.
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// Main loop.
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while (!glfwWindowShouldClose(window)) {
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glfwPollEvents();
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double currentTime = glfwGetTime();
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if (running && (currentTime - lastStepTime) >= stepInterval && !emulator.halted) {
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emulator.step();
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lastStepTime = currentTime;
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}
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ImGui_ImplOpenGL3_NewFrame();
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ImGui_ImplGlfw_NewFrame();
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ImGui::NewFrame();
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// CPU Control Panel.
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ImGui::Begin("CPU Control");
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if (ImGui::Button("Reset")) {
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emulator.reset();
|
||
emulator.loadProgram(program);
|
||
running = false;
|
||
}
|
||
ImGui::SameLine();
|
||
if (ImGui::Button("Start"))
|
||
running = true;
|
||
ImGui::SameLine();
|
||
if (ImGui::Button("Stop"))
|
||
running = false;
|
||
ImGui::SameLine();
|
||
if (ImGui::Button("Step") && !emulator.halted)
|
||
emulator.step();
|
||
ImGui::Text("PC: 0x%08X", emulator.pc);
|
||
if (emulator.halted)
|
||
ImGui::TextColored(ImVec4(1, 0, 0, 1), "CPU Halted");
|
||
ImGui::Separator();
|
||
|
||
// Registers display.
|
||
if (ImGui::BeginTable("Registers", 4, ImGuiTableFlags_Borders | ImGuiTableFlags_RowBg)) {
|
||
ImGui::TableSetupColumn("Reg");
|
||
ImGui::TableSetupColumn("Value");
|
||
ImGui::TableSetupColumn("Reg");
|
||
ImGui::TableSetupColumn("Value");
|
||
ImGui::TableHeadersRow();
|
||
for (int i = 0; i < 32; i += 2) {
|
||
ImGui::TableNextRow();
|
||
ImGui::TableSetColumnIndex(0);
|
||
ImGui::Text("x%d", i);
|
||
ImGui::TableSetColumnIndex(1);
|
||
ImGui::Text("0x%08X", emulator.registers[i]);
|
||
ImGui::TableSetColumnIndex(2);
|
||
ImGui::Text("x%d", i+1);
|
||
ImGui::TableSetColumnIndex(3);
|
||
ImGui::Text("0x%08X", emulator.registers[i+1]);
|
||
}
|
||
ImGui::EndTable();
|
||
}
|
||
ImGui::Text("Flags: Z[%d] N[%d] C[%d] O[%d]",
|
||
emulator.flags.zero, emulator.flags.negative,
|
||
emulator.flags.carry, emulator.flags.overflow);
|
||
ImGui::Separator();
|
||
|
||
// Disassembly view.
|
||
ImGui::BeginChild("Disassembly", ImVec2(0, 150), true);
|
||
ImGui::Text("Disassembly:");
|
||
for (int i = 0; i < 10; i++) {
|
||
uint32_t addr = emulator.pc + i * 4;
|
||
std::string line = emulator.disassembleInstruction(addr);
|
||
if (i == 0)
|
||
ImGui::TextColored(ImVec4(1, 1, 0, 1), "0x%08X: %s", addr, line.c_str());
|
||
else
|
||
ImGui::Text("0x%08X: %s", addr, line.c_str());
|
||
}
|
||
ImGui::EndChild();
|
||
ImGui::End();
|
||
|
||
// Memory Viewer in a grid.
|
||
ImGui::Begin("Memory Viewer");
|
||
const int columns = 16, rows = 16;
|
||
if (ImGui::BeginTable("MemoryGrid", columns, ImGuiTableFlags_Borders)) {
|
||
for (int col = 0; col < columns; col++) {
|
||
ImGui::TableSetupColumn("");
|
||
}
|
||
ImGui::TableHeadersRow();
|
||
int wordIndex = 0;
|
||
for (int r = 0; r < rows; r++) {
|
||
ImGui::TableNextRow();
|
||
for (int c = 0; c < columns; c++) {
|
||
ImGui::TableSetColumnIndex(c);
|
||
if (wordIndex < emulator.memory.size())
|
||
ImGui::Text("0x%08X", emulator.memory[wordIndex]);
|
||
else
|
||
ImGui::Text("----");
|
||
wordIndex++;
|
||
}
|
||
}
|
||
ImGui::EndTable();
|
||
}
|
||
ImGui::End();
|
||
|
||
// Terminal screen to display ECALL outputs.
|
||
ImGui::Begin("Terminal");
|
||
// Optionally, you can add a "Clear" button.
|
||
if (ImGui::Button("Clear"))
|
||
emulator.terminalOutput.clear();
|
||
ImGui::Separator();
|
||
// Display the terminal output in a scrolling region.
|
||
ImGui::BeginChild("ScrollingRegion", ImVec2(0, 150), false, ImGuiWindowFlags_HorizontalScrollbar);
|
||
ImGui::TextUnformatted(emulator.terminalOutput.c_str());
|
||
ImGui::EndChild();
|
||
ImGui::End();
|
||
|
||
// Rendering.
|
||
ImGui::Render();
|
||
int display_w, display_h;
|
||
glfwGetFramebufferSize(window, &display_w, &display_h);
|
||
glViewport(0, 0, display_w, display_h);
|
||
glClearColor(0.45f, 0.55f, 0.60f, 1.00f);
|
||
glClear(GL_COLOR_BUFFER_BIT);
|
||
ImGui_ImplOpenGL3_RenderDrawData(ImGui::GetDrawData());
|
||
glfwSwapBuffers(window);
|
||
}
|
||
|
||
// Cleanup.
|
||
ImGui_ImplOpenGL3_Shutdown();
|
||
ImGui_ImplGlfw_Shutdown();
|
||
ImGui::DestroyContext();
|
||
glfwDestroyWindow(window);
|
||
glfwTerminate();
|
||
return 0;
|
||
}
|